1. Field of the Invention
This invention relates to computing systems, and more particularly, to efficient management of operating modes within a system-on-a-chip (SOC) for optimal power and performance targets.
2. Description of the Relevant Art
The power consumption of modern integrated circuits (IC's) has become an increasing design issue with each generation of semiconductor chips. As power consumption increases, more costly cooling systems such as larger fans and heat sinks must be utilized in order to remove excess heat and prevent IC failure. However, cooling systems increase system costs. The IC power dissipation constraint is not only an issue for portable computers and mobile communication devices, but also for high-performance microprocessors, which may include multiple processor cores, or cores, and multiple pipelines within a core.
A system-on-a-chip (SOC) integrates multiple functions into a single integrated chip substrate. The functions may include digital, analog, mixed-signal and radio-frequency (RF) functions. Typical applications are used in the area of embedded systems. Energy-constrained cellular phones, portable communication devices and entertainment audio/video (A/V) devices are some examples of systems using an SOC. An SOC may use powerful processors, whereby power consumption may significantly rise if not managed.
A power management unit (PMU) for an IC like an SOC may disable portions of the SOC when it detects or is otherwise informed that the portion is unused for a given period of time. Similarly, power-performance states (P-states) may be adjusted based on compute unit usage feedback. These portions usually refer to general-purpose processors, graphics processors, and other processing units (although more gross or finer granularities are possible). Typically, a complex and multi-platform interface controller hub is located off-chip.
When such a platform input/output (I/O) controller hub (PICH) is placed on-die within the SOC, the power management mechanism does not monitor an activity level or a power estimate for the PICH. Rather, the power management mechanism may assume either a constant high power condition or a constant low power condition in the PICH. When a constant high power condition is used, a non-trivial performance loss may occur in the on-die processors. When a constant low power condition is used, thermal throttling may occur due to temperature overages.
In view of the above, efficient methods and systems for efficient management of operating modes within a IC for optimal power and performance targets are desired.